Why use CORTEX M family
instead of 8 and 16 bit MCU

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Systems-on-chip microcontrollers based on the ARM CORTEX M core have garnered a lot of attention in the embedded market-place in the last years.
There is a lot of CORTEX M with:
aggressive price
small footprints
versatile peripheral and memory
blazingly fast execution speeds
In this article I try to explain why CORTEX M family is the better solution for projects for today and for tomorrow.

For those unfamiliar with the family CORTEX we give some preliminary clarifications.
In general, the main features of ARM core are:
Core 32bit
RISC architecture
Excellent relations DMips/Watt
Some years ago, ARM has launched a new generation of its core identified by the name: CORTEX
The family is divided into three subfamilies:
The x indicates that after the letter (A, R, M) is a number that identifies in detail the core.
The family CORTEX M is divided into four subgroups that are: M0, M1, M3 and M4 described below.
The computing power of CORTEX M is in the range from 0.8 DMips/MHz to 1.25 DMips/MHz.
ARM consider obsolete the families: ARM7, ARM9 and ARM11.
Now we analyze in detail the family CORTEX M.

Parts Cost
It is no secret that ARM Cortex M family are pushing the price/performance ratio to heretofore unseen levels.
The main target of comparison between ARM Cortex M family is traditional 8 and 16 bit microcontrollers.
Long considered the cheapest mainstream alternative, 8 bit microcontrollers are facing considerable competitive pressure from ARM Cortex M family.
In general, when the pin-out of the 8/16 bit MCUs are close to 28/32, it should be evaluated also at the CORTEX M family.
STM and NXP Cortex M3 price is under 1$
for 10Kps.

Of course the performance of CORTEX M is minimun double compared to 8 and 16 bit MCU but also the memory occupation is normaly from 10 to 40% less than 8 and 16 bit MCU.
By using Cortex M, as if by magic, it means to solve all the problems of timing that you have usually with 8 and 16 bits.
Often designers who use 8 and 16 bit must take into account the execution times of the main() and of the interrupt routines to avoid loss of asynchronous events. Using CORTEX M these problems do not exist or are extremely rarely.

1,25 DMips/MHz is the performance of Cortex M3 series.

Code size comparison using relative EEMBC CoreMark test size

Comparision between 8/16bit and STM32F0xx (CORTEX M0)

Easy to Use
The architecture of the Cortex M family is very similar to that of normal microcontrollers and also thanks to the libraries, it is very easy to develop applications quickly.
Normally, after a day of training, all my customers have been able to independently develop their own applications.
In the http://www.emcu.it/STM32.html you can find a lot of tutorial concerning the way to use Library, Tools, IDE and so on.

Free Tools
Today you can also use free tools with satisfaction like:
Eclipse + OpenOCD + GCC
This kit is available for Linux and Windows.

Proprietary Tools Cost
The price of proprietary compilers start from 1000€ that is reasonable price for professional tools.
Some of this tools are:

JTAG and SWD interface
All CORTEX M support JTAG interface for software development and debugging but also support SWD (Serial Wire Debug) for
software development and debugging
Serial Wire Debug technology provides a 2-pin debug port, the low pin count and high-performance alternative to JTAG.
More info are here.
An example of low cost tool is STM32 Discovery.

Today 80% of applications are developed in a traditional way but it is often convenient to use the
RTOS (real-time operating system) that simplify the writing of the program.
Today it is available also FreeRTOS for Cortex M family.

Proprietary RTOS
There are lots of proprietary RTOS, to find out more click here.

Compatibility from different Cortex M vendors
Apart from the pinout difference of the CORTEX M from one vendor to another:
STM, FREESCALE, NXP, ANALOG, etc., the main differences are in the peripherals around the MCU.
Who has white hairs, surely remembers the Core-51 available from different vendors.
In the period of Core-51, all of us thought to develop hardware and then we looked for a Core-51 that had all the necessary peripherals.
This because all SW engineers knew the Core-51 and the main work was to develop the driver for the different peripherals.
This allowed us to remain unlinked to a particular vendors.
The same is today by using Cortex M.
Today is easier because there is the CMSIS (Cortex Microcontroller Software Interface Standard) specification that facilitates the translation of the SW by a vendor to another.
Today a lot of vendors provide library CMSIS compliant (see STM library).

Energy Efficiency
Today there is a particularly strong energy problem for which all equipments should consume as little as possible.
Cortex M series run at lower MHz or with shorter activity periods:
Architected support for sleep modes
Work smarter, sleep longer than 8/16-bit

Comparing Cortex-M processors
The Cortex-M family is an ideal solution for ranges of compatible, easy to use embedded devices such as microcontrollers (MCU) where different cost, power and performance considerations must be made.
Each processor delivers an optimal trade-off for a broad embedded application range.

Cortex-M processors are all binary upwards compatible, enabling software reuse and a seamless progression from one Cortex-M processor to another.

For more info contact your SILICA local FAE


The following list shows the debug hardware interfaces that can be available for each of the Cortex M processors, and an explanation of each follows:

Cortex M0: JTAG / SWD
Cortex M1: JTAG (JTAG-DP) / SWD (SW-DP)
Cortex M3: JTAG / SWD / SWO / ETM TraceData
Cortex M4: JTAG / SWD / SWO / ETM M4 (v3.5 std)

JTAG: This is more of a legacy interface for software development and debugging and is also used for manufacturing test. In most instances, it is better to turn this off and choose serial wire debug (SWD) instead for debugging software. In ARM-based debuggers, there is typically a menu where you choose between this and SWD, exclusive to each other.
SWD: serial wire debug. An enhancement to JTAG, where commands are transferred at a high rate of speed between the debugger and the interface to the core. Data from watchpoint and breakpoint registers is transferred.
SWO: serial wire output: This is a special pin that allows additional data transfer off the microcontroller while it is running. Typically, data is sent over this port without having to stop or burden the processor core. Facilities for a printf() type of output and being able to look at memory regions while running are used.
ETM: Up to four additional "tracedata" pins are used to reflect every instruction that is executing to the debugger. This trace data can be used to capture the events leading up to a defined event, or also used to provide code coverage statistics (important for vital software development) or execution information. For Cortex M4, this interface is expanded to include FIFO queues for information, counters, differing trigger definitions, and other upgraded features over Cortex M3.

CMSIS - Cortex Microcontroller Software Interface Standard

The ARM Cortex™ Microcontroller Software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex-M processor series.  The CMSIS enables consistent and simple software interfaces to the processor for interface peripherals, real-time operating systems, and middleware, simplifying software re-use, reducing the learning curve for new microcontroller developers and reducing the time to market for new devices.
The standard is fully scalable to ensure that it is suitable for all Cortex-M processor series microcontrollers from the smallest 8 KB device up to devices with sophisticated communication peripherals such as Ethernet or USB-OTG. 
(The CMSIS memory requirement for the Core Peripheral Access Layer is less the 1 KB code, less than 10 Bytes RAM).

Documentation for Cortex-M device users

Software development tools for Cortex-M device users

Find Cortex-M based microcontrollers

Cortex-M Series Processor Documentation

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